bioRxivNeurosciencePreprint
A single cortical circuit implements fast and slow visual search
Mattia F. PagnottaiD, Haojun Zhuang, S. J. Katarina SlamaiD, David King‐StephensiD, Kenneth D. LaxeriD, Tor EndestadiD, Anne‐Kristin SolbakkiD, Jack J. LiniD, Robert Thomas KnightiD
Abstract
How the brain produces different behaviors from a fixed anatomical substrate is a foundational question in neuroscience. The dominant account holds that behavioral flexibility requires distinct neural circuits: dedicated systems selectively recruited for different processing modes. An alternative proposes that flexibility arises not from switching between circuits, but from dynamically controlling the speed at which a shared circuit operates. Here, we test this account directly using intracranial EEG recordings from nineteen human patients performing two visual search tasks of markedly different difficulty: an easy color-singleton search and a difficult orientation search, a fast vs. slow dissociation attributed for four decades to distinct anatomical and oscillatory neural systems. We show that both search tasks recruit the same cortical regions, oscillatory frequencies, and processing hierarchy. Dynamic time warping reveals that the two neural trajectories are time-stretched versions of one another; the same temporal scaling appears within each condition between faster and slower trials, indexing response speed rather than the distinction between tasks. Alpha-band oscillations (~8-10 Hz) support this temporal scaling through two coordinated mechanisms: synchronizing activity across a posterior cortical network and phase-gating local high-frequency activity (70-150 Hz) within those regions at the same preferred phase in both conditions. These findings establish that, for the two tasks studied here, fast and slow visual search are not implemented by selecting between distinct dedicated circuits, but by adjusting the speed of a single alpha-coordinated architecture. The same principle may apply to other search tasks, and to other domains in which dual-process architectures have been invoked, a testable prediction for future studies.
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