Optimization of heuristic logic synthesis by iteratively reducing circuit substructures using a database of optimal implementations
Anh Phong Tran, Dhruv D. Jatkar, M. Ali Al-Radhawi, Elizabeth Ann Ernst, Eduardo D. Sontag
This paper improves heuristic logic synthesis by using a database of optimal 4-input Boolean implementations to reduce gate count in larger circuits, achieving average improvements of 5.16% and 4.54% for 5- and 6-input circuits respectively.
bioRxiv · Nov 28, 2025 · PreprintSynthetic Biology