bioRxivSynthetic BiologyPreprint
Exploring the design space of recombinase logic circuits.
Sarah GuiziouiD, Guillaume Pérution-KihliiD, Federico UllianaiD, Michel LeclèreiD, Jerome BonnetiD
Abstract
Logic circuits operating in living cells are generally built by mimicking electronic layouts, and scale-up is accomplished using additional layers of elementary logic gates like NOT and NOR gates. Recombinase-based logic, in which logic is implemented using DNA inversion or excision, allows for highly efficient, compact and single-layer design architectures. However, recombinase logic architectures depart from electronic design principles, and gate design performed empirically is challenging for an increasing number of inputs. Here we used a combinatorial approach to explore the design space of recombinase logic devices. We generated combinations and permutations of recombination sites, genes, and regulatory elements, for a total of ~19 million designs supporting the implementation of all 2- and 3-input logic functions and up to 92% of 4-input logic functions. We estimated the influence of different design constraints on the number of executable functions, and found that the use of DNA inversion and transcriptional terminators were key factors to implement the vast majority of logic functions. We provide a user-friendly interface, called RECOMBINATOR (http://recombinator.lirmm.fr/index.php), that enable users to navigate the design space of recombinase-based logic, find architectures implementing a specific logic function and sort them according to various biological criteria. Finally, we define a set of 16 architectures from which all 256 3-input logic functions can be derived. This work provides a theoretical foundation for the systematic exploration and design of single-layer recombinase logic devices.\n\n\n\nO_FIG O_LINKSMALLFIG WIDTH=200 HEIGHT=55 SRC=\"FIGDIR/small/711374v2_ufig1.gif\" ALT=\"Figure 1\">\nView larger version (14K):\norg.highwire.dtl.DTLVardef@799feborg.highwire.dtl.DTLVardef@f22dc2org.highwire.dtl.DTLVardef@19a1d10org.highwire.dtl.DTLVardef@ea3b9a_HPS_FORMAT_FIGEXP M_FIG C_FIG
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