Anastasia Deckard

This paper introduces DART, a DBTL loop for synthetic genetic circuit design, showing that complex circuits can be more robust and reproducible than simpler ones in budding yeast.

The paper develops a computational method to predict synthetic circuit robustness across growth conditions and validates it with experimental results in budding yeast.

The paper introduces a computational pipeline to identify core genetic networks from time-series data by iteratively reducing hypotheses, validated on synthetic and yeast cell-cycle data.

The paper identifies core gene regulatory network components across species by analyzing transcriptome dynamics, revealing shared features in GRNs controlling periodic biological processes.

The paper replicates yeast-based logic circuit design assessments using a high-throughput robotic framework, generating more flow cytometry data than the original study.