Justin D. Vrana

Robustness and reproducibility of simple and complex synthetic logic circuit designs using a DBTL loop

This paper introduces DART, a DBTL loop for synthetic genetic circuit design, showing that complex circuits can be more robust and reproducible than simpler ones in budding yeast.

Computational Prediction of Synthetic Circuit Function Across Growth Conditions

The paper develops a computational method to predict synthetic circuit robustness across growth conditions and validates it with experimental results in budding yeast.

Highly-Automated, High-Throughput Replication of Yeast-based Logic Circuit Design Assessments

The paper replicates yeast-based logic circuit design assessments using a high-throughput robotic framework, generating more flow cytometry data than the original study.