Konstantin Mischaikow

This paper introduces DART, a DBTL loop for synthetic genetic circuit design, showing that complex circuits can be more robust and reproducible than simpler ones in budding yeast.

The paper develops a computational method to predict synthetic circuit robustness across growth conditions and validates it with experimental results in budding yeast.

The paper introduces a computational pipeline to identify core genetic networks from time-series data by iteratively reducing hypotheses, validated on synthetic and yeast cell-cycle data.